郑州网站制作营销,标书制作文员主要干什么,免费奖励代码网站,宣城市住房和城乡建设局网站首页接下来的分析和实践非常粗糙#xff0c;因为跟之前一样的分析流程#xff0c;不再多说了#xff0c;如果前面真的掌握#xff0c;这里不看也罢。
分析
先看beq指令。
ALU输入的是rs和rt#xff0c;不输入imm#xff0c;进行subu操作#xff0c;判断是否为zero#x…接下来的分析和实践非常粗糙因为跟之前一样的分析流程不再多说了如果前面真的掌握这里不看也罢。
分析
先看beq指令。
ALU输入的是rs和rt不输入imm进行subu操作判断是否为zero输出zero信号。
控制器增加Branch信号识别beq指令当zero和Branch同时成立就可以跳转目标地址是PC 4 (sign-extend)offset。
bne指令同理。
实现
ALU
ALU增加zero输出如果rs - rt 0zero 0即rs rt对应beq指令若zero 1对应bne指令。
增加offset输出是offset字段符号扩展并左移2位后的结果用于和pc 4在pc模块相加。
pc
增加offset数据信号以及Branch和nBranch跳转信号和zero信号。
control
增加Branch和nBranch信号。
Datapath
最后更改顶层数据通路。
注意一个大坑
我们设计的数据通路取指需要2个周期这个时候跳转指令的pc其实已经变成了pc 8了如果再执行 pc 4 offset就会执行原本应该执行的下下条指令这是错误的。
因此我们应该将PC 4的值与当前执行的PC指令一起传过去。这里偷懒起见直接在原来基础上PC - 8以避开2个时钟周期的取指延迟。
关于取指延迟对需要pc值的指令的影响可能有不少后续再说 可以看见ROM延迟两个时钟周期因此说刚才的解决方案也不对……即便能够跳转到正确的指令但是在此之前如果有指令不需要执行但是也被执行了每一个b跳转指令最多被错误地执行2条指令。
……这可咋办呢这是单周期又不是流水线……如何改变局面?
后续再说。
类比这个情况下似乎是类流水线了分为取指和执行2个阶段……嗯回头想想解决方案吧
尝试一
取指占2个时钟周期执行占1个时钟周期每条指令执行占3个时钟周期。
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/12 20:31:59
// Design Name:
// Module Name: pc_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module pc_1(input clk,input rst_n,// pc datainput [31:0] pcOrigin, // The PC value is from pcOld.input [31:0] JrPC, // jr instruction,from reg files.// pc controlinput Jrn, // jr instruction.// beq bneinput [31:0] offset,input zero,input Branch,input nBranch,output [31:0] pcOld);reg [31:0] pc 0;
assign pcOld pc;// judge validity of beq/bne instruction
reg isBranch;
always (*)
beginif((zero 1) (Branch 1)) // beq validbeginisBranch 1;endelse if((zero 0) (nBranch 1)) // bne validbeginisBranch 1;endelsebeginisBranch 0;end
end// select new pc value
reg [31:0] pcSelect; // new pc data
always (*)
begincase({Jrn,Branch,nBranch})3b000: // pc 4pcSelect pcOrigin 4;3b100: // jrpcSelect JrPC;3b010: // beqpcSelect pcOrigin 4 offset; /**** NOTE ****/3b001: // bne // fetch instruction waste 2 clock cycles,then execute 1 cyclepcSelect pcOrigin 4 offset; /**** NOTE ****/default:pcSelect 0;endcase
end// counter: wait 2 clock cycles to fetch instruction
reg counter 0;
always (posedge clk)
beginif(counter 1)counter 0;elsecounter counter 1;
end// Update PC register
always (posedge clk)
beginif(rst_n 1) // Xilinx 官方推荐reset 高电平有效beginpc 0;endelse if(counter 1)beginpc pcSelect;endelsebeginpc 0;end
endendmodule
加了计时器但是还是解决不了问题…… 现在能够满足当前执行的指令pc值是下一条指令的地址但是更新存在问题依然避不开的是取指需要2个时钟周期。
问题解决让CPU与Memory的时钟频率不一样
首先我们需要知道CPU和Memory内外有别它们的clk频率完全可以不一样这样我们让Memory的频率快一点使得CPU在一个时钟周期内完成取指和执行就满足了我们的设计要求。
这里需要强化一个概念我们需要知道单周期CPU指的是CPU在一个时钟周期内能够完成一条指令的取指和执行操作单周期指的是CPU而不是Memory。
实践笔记5插叙内外有别之CPU和Memory
1 解决方案
1.1 增加时钟分频器 使用MMCM不是PLL。 注意此IP核有启动时间。 另外……当仿真没有信号的时候看看是不是没有加信号……
1.2 分别对待CPU与Memory的时钟频率
CPU时钟频率20MHz 内存时钟频率100MHz
1.3 其他部件的实现
PC
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/12 20:31:59
// Design Name:
// Module Name: pc_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module pc_1(input clk,input rst_n,// pc datainput [31:0] pcOrigin, // The PC value is from pcOld.input [31:0] JrPC, // jr instruction,from reg files.// pc controlinput Jrn, // jr instruction.// beq bneinput [31:0] offset,input zero,input Branch,input nBranch,output [31:0] pcOld);reg [31:0] pc 0;
assign pcOld pc;// judge validity of beq/bne instruction
reg isBranch;
always (*)
beginif((zero 1) (Branch 1)) // beq validbeginisBranch 1;endelse if((zero 0) (nBranch 1)) // bne validbeginisBranch 1;endelsebeginisBranch 0;end
end// select new pc value
reg [31:0] pcSelect; // new pc data
always (*)
begincase({Jrn,isBranch})2b00: // pc 4pcSelect pcOrigin 4;2b10: // jrpcSelect JrPC;// fetching 1 instruction wastes 2 clock cycles(memory), and// executing the instruction needs 1 clock cycle(CPU).// NOTE:the frequency of two clocks is different. 2b01: // beq bnepcSelect pcOrigin 4 offset; default:pcSelect 0;endcase
end// Update PC register
always (posedge clk)
beginif(rst_n 1) // Xilinx suggestreset high level effectivebeginpc 0;endelsebeginpc pcSelect;end
endendmodule
Control
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/14 22:30:48
// Design Name:
// Module Name: control_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module control_1(input [5:0] op,input [5:0] func,output reg RegWrite,output reg Sftmd, // indicate the instruction is sll/srl/sraoutput reg [3:0] ALUop,output reg Jrn, // jr instructionoutput reg Lui, // lui instructionoutput reg RegDst,output reg ALUSrc,output reg Zero_sign_ex,output reg Branch, // beqoutput reg nBranch // bne);always (*)
begincase(op)6b000000: R-type begincase (func)6b100000: // addbeginRegWrite 1;Sftmd 0;ALUop 4b0000;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100001: // addubeginRegWrite 1;Sftmd 0;ALUop 4b0001;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100010: // subbeginRegWrite 1;Sftmd 0;ALUop 4b0010;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100011: // sububeginRegWrite 1;Sftmd 0;ALUop 4b0011;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100100: // andbeginRegWrite 1;Sftmd 0;ALUop 4b0100;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100101: // orbeginRegWrite 1;Sftmd 0;ALUop 4b0101;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100110: // xorbeginRegWrite 1;Sftmd 0;ALUop 4b0110;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b100111: // norbeginRegWrite 1;Sftmd 0;ALUop 4b0111;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b101010: // sltbeginRegWrite 1;Sftmd 0;ALUop 4b1000;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b101011: // sltubeginRegWrite 1;Sftmd 0;ALUop 4b1001;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000100: // sllvbeginRegWrite 1;Sftmd 0;ALUop 4b1010;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000110: // srlvbeginRegWrite 1;Sftmd 0;ALUop 4b1011;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000111: // sravbeginRegWrite 1;Sftmd 0;ALUop 4b1100;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000000: // sllbeginRegWrite 1;Sftmd 1;ALUop 4b1010;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000010: // srlbeginRegWrite 1;Sftmd 1;ALUop 4b1011;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000011: // srabeginRegWrite 1;Sftmd 1;ALUop 4b1100;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;end6b001000: // jrbeginRegWrite 0;Sftmd 0;ALUop 4b1111;Jrn 1;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;enddefault:beginRegWrite 0;Sftmd 0;ALUop 4b1111;Jrn 0;Lui 0;RegDst 1;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;endendcaseend/*************** I-type ***************/6b001000: // addibeginALUop 4b0000;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 1;Branch 0;nBranch 0;end6b001001: // addiubeginALUop 4b0001;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 1;Branch 0;nBranch 0;end6b001100: // andibeginALUop 4b0100;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 0;Branch 0;nBranch 0;end6b001101: // oribeginALUop 4b0101;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 0;Branch 0;nBranch 0;end6b001110: // xoribeginALUop 4b0110;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 0;Branch 0;nBranch 0;end6b001111: // lui note beginALUop 4b1101;RegWrite 1;Sftmd 0;Jrn 0;Lui 1;RegDst 0;ALUSrc 1;Zero_sign_ex 0;Branch 0;nBranch 0;end6b001010: // sltibeginALUop 4b1000;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 1;Branch 0;nBranch 0;end6b001011: // sltiubeginALUop 4b1001;RegWrite 1;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 1;Zero_sign_ex 0;Branch 0;nBranch 0;end6b000100: // beqbeginALUop 4b0011;RegWrite 0;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 0;Zero_sign_ex 1;Branch 1;nBranch 0;end6b000101: // bnebeginALUop 4b0011;RegWrite 0;Sftmd 0;Jrn 0;Lui 0;RegDst 0;ALUSrc 0;Zero_sign_ex 1;Branch 0;nBranch 1;enddefault:beginRegWrite 0;Sftmd 0;ALUop 4b1111;Jrn 0;Lui 0;RegDst 0;ALUSrc 0;Zero_sign_ex 0;Branch 0;nBranch 0;endendcase
endendmoduleALU
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/14 22:30:23
// Design Name:
// Module Name: ALU_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module ALU_1(// datainput [31:0] A,input [31:0] B,input [4:0] shamt,// controlinput [3:0] ALUop,input Sftmd, // shift instruction control/*** I-type ***/input [15:0] imm, // data// controlinput Lui, // 1:lui instructioninput ALUSrc, // 1:imm calculateinput Zero_sign_ex, // 0:zero extension; 1:sign extensionoutput reg [31:0] ALUresult,// beq bne output [31:0] offset, output zero // ALUresult 0 zero 1;);// convert A and B to signed numbers
wire signed [31:0] A_signed A;
wire signed [31:0] B_signed;
wire signed [31:0] B_signed_origin B; // for sra instruction// for shift instructions
// select data: if (Sftmd 1) input shamt else input rs
wire [31:0] A_or_Shift (Sftmd 0) ? A : {27b0,shamt};/*** I-type: data select ***/// immediate data extension and select
wire [31:0] zero_imm_ex {16b0,imm};
wire [31:0] sign_imm_ex (imm[15] 1)? {16hffff,imm}: {16b0,imm}; // NOTE: 16b1 is incorrect
wire [31:0] imm_input (Zero_sign_ex 0)? zero_imm_ex: sign_imm_ex;// R[rt] or imm extension
wire [31:0] B_select (ALUSrc 0)? B: imm_input;
assign B_signed B_select;// output: (sign extension)offset 2
assign offset imm_input 2;/* calculate */
always (*)
begincase (ALUop)4b0000: // add addibeginALUresult A B_select;end4b0001: // addu addiubeginALUresult A B_select;end4b0010: // subbeginALUresult A - B;end4b0011: // sububeginALUresult A - B;// zero ((A-B) 0)? 1: 0; // beqend4b0100: // and andibeginALUresult A B_select;end4b0101: // or oribeginALUresult A | B_select;end4b0110: // xor xoribeginALUresult A ^ B_select;end4b0111: // nor noribeginALUresult ~(A | B_select);end4b1000: // slt slti // note:********signed********//beginif(A_signed B_signed)ALUresult 1;elseALUresult 0;end4b1001: // sltu sltiubeginif(A B_select)ALUresult 1;elseALUresult 0;end4b1010: // sllv 10 /*** note: not B_select ***/beginALUresult B A_or_Shift; // NOTE: not A B!end4b1011: // srlvbeginALUresult B A_or_Shift; // NOTE: not A B!end4b1100: // srav // note: ******signed*******//beginALUresult B_signed_origin A_or_Shift; // NOTE: not A_signed B!end4b1101: // luibeginALUresult (Lui 1)? {imm,16b0}: 0;enddefault:beginALUresult 0;endendcase
endassign zero (ALUresult 0)? 1: 0;endmodule
注意ALU的zero信号就是判断ALUresult是不是0是的话就是1。
Datapath
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/27 11:41:34
// Design Name:
// Module Name: datapath_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description: 仅仅实现了几个简单的R类指令的最简单的数据通路不与外界交互
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module datapath_1(input clk, // 100MHz input rst_n,output [31:0] result // 测试syntheses没有输出的模块是恐怖的);/
/******* clk *******/
/// cpu_clk Inputs
// reg clk; // cpu_clk Outputs
wire clk_div; // 20Mhzcpu_clk u_cpu_clk (.clk_in1 ( clk ),.clk_out1 ( clk_div )
);//
/******** PC ********/
//// pc_1 Inputs
wire Jrn;
wire [31:0] JrPC;wire [31:0] offset_in;
wire zero_in;
wire Branch_in;
wire nBranch_in;// pc_1 Outputs
wire [31:0] pcOld;pc_1 u_pc_1 (.clk ( clk_div ),.rst_n ( rst_n ),.pcOrigin ( pcOld ),.JrPC ( JrPC ),.Jrn ( Jrn ),.offset ( offset_in ),.zero ( zero_in ),.Branch ( Branch_in ),.nBranch ( nBranch_in ),.pcOld ( pcOld ));///
/******** Instruction ROM ********/
///// blk_mem_gen_0 Inputs
// wire [13:0] addra pcOld[15:2];// blk_mem_gen_0 Outputs // instructions
wire [31:0] instruction;blk_mem_gen_0 u_blk_mem_gen_0 (.clka ( clk ),.addra ( pcOld[15:2] ),.douta ( instruction ));/
/******** Reg Files ********/
/// reg_files_1 Inputs
wire [31:0] ALUresult;/// wire [4:0] rA instruction[25:21];
/// wire [4:0] rB instruction[20:16];
/// wire [4:0] rW instruction[15:11];
/// wire [31:0] writeData ALUresult;
wire RegWrite;
wire RegDst_in;// reg_files_1 Outputs
wire [31:0] A; // rs
wire [31:0] B; // rt
assign JrPC A;reg_files_1 u_reg_files_1 (.clk ( clk_div ),.rst_n ( rst_n ),.rA ( instruction[25:21] ),.rB ( instruction[20:16] ),.rW ( instruction[15:11] ),.writeData ( ALUresult ),.RegWrite ( RegWrite ),.RegDst ( RegDst_in ),.A ( A ),.B ( B ));///
/******** ALU ********/
///// ALU_1 Inputs
// wire [31:0] A;
// wire [31:0] B;
wire [3:0] ALUop;
wire Sftmd;wire [15:0] imm instruction[15:0];
wire Lui_in;
wire ALUSrc_in;
wire Zero_sign_ex_in;// ALU_1 Outputs
// wire [31:0] ALUresult writeData; // NoteError
wire [31:0] offset;
wire zero;assign offset_in offset;
assign zero_in zero;ALU_1 u_ALU_1 (.A ( A ),.B ( B ),.shamt ( instruction[10:6]),.ALUop ( ALUop ),.Sftmd ( Sftmd ),/** I-type **/.imm ( imm ),.Lui ( Lui_in ),.ALUSrc ( ALUSrc_in ),.Zero_sign_ex ( Zero_sign_ex_in ),.ALUresult ( ALUresult ),.offset ( offset ),.zero ( zero ));/
/******** controler ********/
/// control_1 Inputs
// wire [5:0] op instruction[31:26];
// wire [5:0] func instruction[5:0];// control_1 Outputs
// wire RegWrite
// wire [3:0] ALUop;
wire Lui;
wire RegDst;
wire ALUSrc;
wire Zero_sign_ex;
wire Branch;
wire nBranch;// send to Reg Files
assign RegDst_in RegDst;
// send to ALU
assign Lui_in Lui;
assign ALUSrc_in ALUSrc;
assign Zero_sign_ex_in Zero_sign_ex;
// send to pc
assign Branch_in Branch;
assign nBranch_in nBranch;control_1 u_control_1 (.op ( instruction[31:26] ),.func ( instruction[5:0] ),.RegWrite ( RegWrite ),.Sftmd ( Sftmd ),.ALUop ( ALUop ),.Jrn ( Jrn ),// I type.Lui ( Lui ),.RegDst ( RegDst ),.ALUSrc ( ALUSrc ),.Zero_sign_ex ( Zero_sign_ex ),// beq bne.Branch ( Branch ),.nBranch ( nBranch ));assign result ALUresult;endmodule仿真综合实现
成功
还没有开发板下载验证。
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/27 11:41:34
// Design Name:
// Module Name: datapath_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description: 仅仅实现了几个简单的R类指令的最简单的数据通路不与外界交互
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module datapath_1(input clk, // 100MHz input rst_n,output [31:0] result // 测试syntheses没有输出的模块是恐怖的);/
/******* clk *******/
/// cpu_clk Inputs
// reg clk; // cpu_clk Outputs
wire clk_div; // 20Mhzcpu_clk u_cpu_clk (.clk_in1 ( clk ),.clk_out1 ( clk_div )
);//
/******** PC ********/
//// pc_1 Inputs
wire Jrn;
wire [31:0] JrPC;wire [31:0] offset_in;
wire zero_in;
wire Branch_in;
wire nBranch_in;// pc_1 Outputs
wire [31:0] pcOld;pc_1 u_pc_1 (.clk ( clk_div ),.rst_n ( rst_n ),.pcOrigin ( pcOld ),.JrPC ( JrPC ),.Jrn ( Jrn ),.offset ( offset_in ),.zero ( zero_in ),.Branch ( Branch_in ),.nBranch ( nBranch_in ),.pcOld ( pcOld ));///
/******** Instruction ROM ********/
///// blk_mem_gen_0 Inputs
// wire [13:0] addra pcOld[15:2];// blk_mem_gen_0 Outputs // instructions
wire [31:0] instruction;blk_mem_gen_0 u_blk_mem_gen_0 (.clka ( clk ),.addra ( pcOld[15:2] ),.douta ( instruction ));/
/******** Reg Files ********/
/// reg_files_1 Inputs
wire [31:0] ALUresult;/// wire [4:0] rA instruction[25:21];
/// wire [4:0] rB instruction[20:16];
/// wire [4:0] rW instruction[15:11];
/// wire [31:0] writeData ALUresult;
wire RegWrite;
wire RegDst_in;// reg_files_1 Outputs
wire [31:0] A; // rs
wire [31:0] B; // rt
assign JrPC A;reg_files_1 u_reg_files_1 (.clk ( clk_div ),.rst_n ( rst_n ),.rA ( instruction[25:21] ),.rB ( instruction[20:16] ),.rW ( instruction[15:11] ),.writeData ( ALUresult ),.RegWrite ( RegWrite ),.RegDst ( RegDst_in ),.A ( A ),.B ( B ));///
/******** ALU ********/
///// ALU_1 Inputs
// wire [31:0] A;
// wire [31:0] B;
wire [3:0] ALUop;
wire Sftmd;wire [15:0] imm instruction[15:0];
wire Lui_in;
wire ALUSrc_in;
wire Zero_sign_ex_in;// ALU_1 Outputs
// wire [31:0] ALUresult writeData; // NoteError
wire [31:0] offset;
wire zero;assign offset_in offset;
assign zero_in zero;ALU_1 u_ALU_1 (.A ( A ),.B ( B ),.shamt ( instruction[10:6]),.ALUop ( ALUop ),.Sftmd ( Sftmd ),/** I-type **/.imm ( imm ),.Lui ( Lui_in ),.ALUSrc ( ALUSrc_in ),.Zero_sign_ex ( Zero_sign_ex_in ),.ALUresult ( ALUresult ),.offset ( offset ),.zero ( zero ));/
/******** controler ********/
/// control_1 Inputs
// wire [5:0] op instruction[31:26];
// wire [5:0] func instruction[5:0];// control_1 Outputs
// wire RegWrite
// wire [3:0] ALUop;
wire Lui;
wire RegDst;
wire ALUSrc;
wire Zero_sign_ex;
wire Branch;
wire nBranch;// send to Reg Files
assign RegDst_in RegDst;
// send to ALU
assign Lui_in Lui;
assign ALUSrc_in ALUSrc;
assign Zero_sign_ex_in Zero_sign_ex;
// send to pc
assign Branch_in Branch;
assign nBranch_in nBranch;control_1 u_control_1 (.op ( instruction[31:26] ),.func ( instruction[5:0] ),.RegWrite ( RegWrite ),.Sftmd ( Sftmd ),.ALUop ( ALUop ),.Jrn ( Jrn ),// I type.Lui ( Lui ),.RegDst ( RegDst ),.ALUSrc ( ALUSrc ),.Zero_sign_ex ( Zero_sign_ex ),// beq bne.Branch ( Branch ),.nBranch ( nBranch ));assign result ALUresult;endmodule