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module top_module(input clk,input reset,input ena,output pm,output [7:0] hh,output [7:0] mm,…目前写过最长的verilog代码用了将近三个小时编写12h显示的时钟改来改去估计只有我自己看得懂吐血
module top_module(input clk,input reset,input ena,output pm,output [7:0] hh,output [7:0] mm,output [7:0] ss); couter10 couter10_1(clk, reset, ena, ss[3:0]);couter6 couter6_1(clk, reset, ss[3:0]9ena, ss[7:4]);couter10 couter10_2(clk, reset, (ss[7:4]5 ss[3:0]9)ena, mm[3:0]);couter6 couter6_2(clk, reset, (mm[3:0]9 ss[7:4]5 ss[3:0]9)ena, mm[7:4]);couter10_forh couter10_forh_1(clk, reset, (mm[7:4]5 mm[3:0]9 ss[7:4]5 ss[3:0]9)ena,(hh[7:4]1 mm[7:4]5 mm[3:0]9 ss[7:4]5 ss[3:0]9)ena ,hh[3:0]);couter1 couter1_1(clk, reset, (hh[3:0]9 mm[7:4]5 mm[3:0]9 ss[7:4]5 ss[3:0]9)ena,(hh[3:0]2 mm[7:4]5 mm[3:0]9 ss[7:4]5 ss[3:0]9)ena,(hh[3:0]1 mm[7:4]5 mm[3:0]9 ss[7:4]5 ss[3:0]9)ena, hh[7:4],pm);endmodulemodule couter10(input clk, input reset, input ena, output [3:0] q);always(posedge clk)if(reset || (q9ena))q 0;else if(ena)q q 1;elseq q;
endmodulemodule couter6(input clk, input reset, input ena, output [3:0] q);always(posedge clk)if(reset || (q5)ena)q 0;else if(ena)q q 1;elseq q;
endmodulemodule couter10_forh(input clk, input reset, input ena,input reload, output [3:0] q);always(posedge clk)if(reset)q 2; else if(q9ena)q 0; else if(q2reload)q 1; else if(ena)q q 1;elseq q;
endmodulemodule couter1(input clk, input reset,input ena, input reload ,input pmset ,output [3:0] q,output pm);always(posedge clk)if(reset)beginq 1;pm 0;endelse if((q1)pmset)beginq q;pm ~pm;endelse if((q1)reload)beginq 0;pm pm; endelse if(ena)beginq q 1;pm pm;endelsebeginq q;pm pm;end
endmodule